POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

12-BIT DAC

12

12

POWER-DOWN

CONTROL

LOGIC

BUFFER

5k

100k

SCLK

SYNC

REF(+) REF(-)

GND

DAC121S101

DAC121S101QML

SNAS410E – MAY 2008 – REVISED MARCH 2013

www.ti.com

Block Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2)

6.5 V

Voltage on any Input Pin

10 mA

10 mA

1.0 mA

20 mA

Maximum Junction Temperature

175°C

Lead Temperature

CLGA package

(Soldering 10 Seconds)

260°C

Storage Temperature

−65°C to +150°C

Package Weight (Typical)

CLGA package

220 mg

Class 3A (5000 V)

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(2)

All voltages are measured with respect to GND = 0 V, unless otherwise specified

(3)

be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of 10 mA to two.

(4)

(5)

fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).

Obviously, such conditions should always be avoided.

(6)

Human body model is 100 pF capacitor discharged through a 1.5 k

Ω resistor. Machine model is 220 pF discharged through ZERO

Ohms.

2

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