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CD74FCT573 데이터시트(PDF) 1 Page - Texas Instruments |
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CD74FCT573 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 12 page CD74FCT573, CD74FCT573AT BiCMOS OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS744A – JULY 2000 – REVISED JULY 2000 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D BiCMOS Technology With Low Quiescent Power D Buffered Inputs D Input/Output Isolation From VCC D Controlled Output Edge Rates D 48-mA Output Sink Current D Output Voltage Swing Limited to 3.7 V D SCR Latch-Up-Resistant BiCMOS Process and Circuit Design D 3-State Outputs Directly Drive Bus Lines D Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP description The CD74FCT573 and CD74FCT573AT are octal, transparent, D-type latches, designed using a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The CD74FCT573 and CD74FCT573AT are characterized for operation from 0 °C to 70°C. FUNCTION TABLE (each latch) INPUTS OUTPUT OE LE D Q L H H H L HL L L LX Q0 H X X Z Copyright © 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1D 2D 3D 4D 5D 6D 7D 8D GND VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE CD74FCT573 ...M OR SM PACKAGE CD74FCT573AT...E PACKAGE (TOP VIEW) |
유사한 부품 번호 - CD74FCT573_16 |
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유사한 설명 - CD74FCT573_16 |
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