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CD74HC652 데이터시트(PDF) 1 Page - Texas Instruments

부품명 CD74HC652
상세설명  High-Speed CMOS Logic Octal-Bus Transceiver/Registers, Three-State
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CD74HC652 데이터시트(HTML) 1 Page - Texas Instruments

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Data sheet acquired from Harris Semiconductor
SCHS194A
[ /Title (CD74HC652, CD74HCT652)
/Subject (High-Speed CMOS Logic Octal-Bus
Transceiver/Registers, Three-State)
/Author ()
/Keywords ()
/Creator ()
/DOCINFO pdfmark
[ /PageMode /UseOutlines
/DOCVIEW pdfmark
Features
• CD74HC652, CD74HCT652 . . . . . . . . . . . Non-Inverting
• Independent Registers for A and B Buses
• Three-State Outputs
• Drives 15 LSTTL Loads
• Typical Propagation Delay = 12ns at VCC =5V, CL = 15pF
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD74HC652
(PDIP)
CD74HCT652
( SOIC)
TOP VIEW
Description
The CD74HC652 and CD74HCT652 three-state, octal-bus
transceiver/registers use silicon-gate CMOS technology to
achieve operating speeds similar to LSTTL with the low power
consumption of standard CMOS integrated circuits. The
CD74HC652 and CD74HCT652 have non-inverting outputs.
These devices consists of bus transceiver circuits, D-type flip-
flops,
and
control
circuitry
arranged
for
multiplexed
transmission of data directly from the data bus or from the
internal storage registers. Output Enables OEAB and OEBA
are provided to control the transceiver functions. SAB and
SBA control pins are provided to select whether real-time or
stored data is transferred. The circuitry used for select control
will eliminate the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time
data. A LOW input level selects real-time data, and a HIGH
selects stored data. The following examples demonstrates the
four fundamentals bus-management functions that can be
performed with the octal-bus transceivers and registers.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by low-to-high transitions at the appropriate
clock pins (CAB or CBA) regardless of the select of the control
pins. When SAB and SBA are in the real-time transfer mode, it
is also possible to store data without using the D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high
impedance, each set of bus lines will remain at its last state.
1
2
3
4
5
6
7
8
9
10
11
12
CAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
A6
A7
GND
16
17
18
19
20
21
22
23
24
15
14
13
VCC
SBA
OEBA
B0
B1
B3
B5
B6
B7
CBA
B2
B4
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD74HC652EN
-55 to 125
24 Ld PDIP
CD74HCT652M
-55 to 125
24 Ld SOIC
CD74HCT652M96
-55 to 125
24 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
February 1998 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD74HC652,
CD74HCT652
High-Speed CMOS Logic
Octal-Bus Transceiver/Registers, Three-State


유사한 부품 번호 - CD74HC652_15

제조업체부품명데이터시트상세설명
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유사한 설명 - CD74HC652_15

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