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CDC509 데이터시트(PDF) 1 Page - Texas Instruments |
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CDC509 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 13 page CDC509 3.3V PHASELOCK LOOP CLOCK DRIVER SCAS576C − JULY 1996 − REVISED DECEMBER 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Use CDCVF2509A as a Replacement for this Device D Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications D Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs D Separate Output Enable for Each Output Bank D External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input D No External RC Network Required D Operates at 3.3-V VCC D Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package NOT RECOMMENDED FOR NEW DESIGNS description The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDC509 is characterized for operation from 0 °C to 70°C. FUNCTION TABLE INPUTS OUTPUTS 1G 2G CLK 1Y (0:4) 2Y (0:3) FBOUT X X L L L L L LHL LH L HH L HH H LH H LH H H H H H H Copyright 1996 − 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CLK AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FBIN 1 2 3 4 5 6 7 8 9 10 11 12 AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FBOUT 24 23 22 21 20 19 18 17 16 15 14 13 PW PACKAGE (TOP VIEW) |
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