CDC924

133MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3STATE OUTPUTS

SCAS607B − NOVEMBER 1998 − REVISED JULY 2005

11

POST OFFICE BOX 655303

APIC

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ten1

Output enable time

SEL133/100

APICx

f(APIC) = 16.67 MHz

6

10

ns

tdis1

Output disable time

SEL133/100

APICx

f(APIC) = 16.67 MHz

8

10

ns

tc

APIC clock period†

f(APIC) = 16.67 MHz

60

60.24

60.6

ns

Cycle to cycle jitter

f(CPU) = 100 or 133 MHz

400

ps

Duty cycle

f(APIC) = 16.67 MHz

45%

55%

tsk(o)

APIC bus skew

APICx

APICx

f(APIC) = 16.67 MHz

30

100

ps

tsk(p)

APIC pulse skew

APICn

APICn

f(APIC) = 16.67 MHz

3

ns

t(off)

APIC clock to CPU clock offset,

rising edge

APICx

CPUx

−1.5

−4

ns

tw1

Pulse duration width, high

f(APIC) = 16.67 MHz

25.5

28

ns

tw2

Pulse duration width, low

f(APIC) = 16.67 MHz

25.3

29.2

ns

tr

Rise time

VO = 0.4 V to 2 V

0.4

1.6

2.1

ns

tf

Fall time

VO = 0.4 V to 2 V

0.4

1.2

1.7

ns

† The average over any 1-µs period of time is greater than the minimum specified period.

3V66

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ten1

Output enable time

SEL133/100

3V66x

f(3V66) = 66 MHz

6

10

ns

tdis1

Output disable time

SEL133/100

3V66x

f(3V66) = 66 MHz

8

10

ns

tc

3V66 clock period†

f(3V66) = 66 MHz

15

15.06

15.3

ns

Cycle to cycle jitter

f(CPU) = 100 or 133 MHz

400

ps

Duty cycle

f(3V66) = 66 MHz

45%

55%

tsk(o)

3V66 bus skew

3V66x

3V66x

f(3V66) = 66 MHz

50

150

ps

tsk(p)

3V66 pulse skew

3V66n

3V66n

f(3V66) = 66 MHz

2.6

ns

t(off)

3V66 clock to CPU clock offset

3V66x

CPUx

0

−0.75

−1.5

ns

t(off)

3V66 clock to PCI clock offset, rising edge

1.2

2.1

3

ns

tw1

Pulse duration width, high

f(3V66) = 66 MHz

5.2

ns

tw2

Pulse duration width, low

f(3V66) = 66 MHz

5

ns

tr

Rise time

VO = 0.4 V to 2 V

0.5

1.5

2

ns

tf

Fall time

VO = 0.4 V to 2 V

0.5

1.5

2

ns

† The average over any 1-µs period of time is greater than the minimum specified period.