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CDC925DL 데이터시트(PDF) 9 Page - Texas Instruments |
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CDC925DL 데이터시트(HTML) 9 Page - Texas Instruments |
9 / 19 page CDC925 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS633 – JULY 28, 1999 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PCIx, PCI_F, 3V66x (Type 5) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage VDD = min to max, IOH = – 1 mA VDD – 0.1 V V OH gg VDD = 3.135 V, IOH = –18 mA 2.4 VOL Low level output voltage VDD = min to max, IOL = 1 mA 0.1 V VOL Low-level output voltage VDD = 3.135 V, IOL = 12 mA 0.15 0.4 V VDD = 3.135 V, VO = 1 V –33 –53 IOH High-level output current VDD = 3.3 V, VO = 1.65 V –53 mA VDD = 3.465 V, VO = 3.135 V –16 –33 VDD = 3.135 V, VO = 1.95 V 30 67 IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 70 mA VDD = 3.465 V, VO = 0.4 V 27 49 CO Output capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7.5 pF ZO Output impedance High state VO = 0.5 VDD, VO/IOH 12 31 55 Ω ZO Output impedance Low state VO = 0.5 VDD, VO/IOL 12 24 55 Ω † All typical values are measured at their respective nominal VDD values. switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Overshoot/undershoot GND – 0.7 V VDD + 0.7 V V Ring back VIL – 0.1 V VIH + 0.1 V V Stabilization time, PWR_DWN to PCIx f(CPU) = 133 MHz 0.05 3 ms tdis3 Disable time, PWR_DWN to PCIx f(CPU) = 133 MHz 50 ns Stabilization time, PWR_DWN to CPUx f(CPU) = 133 MHz 0.03 3 ms tdis4 Disable time, PWR_DWN to CPUx f(CPU) = 133 MHz 50 ns Stabilization time† After SEL1, SEL0 3 ms Stabilization time† After power up 3 ms † Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification. |
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