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AD7273BRM 데이터시트(PDF) 7 Page - Analog Devices

부품명 AD7273BRM
상세설명  3MSPS,10-/12-Bit ADCs in 8-Lead TSOT
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REV. PrB
PRELIMINARYTECHNICALDATA
Preliminary Technical Data
AD7273/AD7274
Figure 5. AD7274 Serial Interface Timing Diagram
Timing Example 1
From Figure 6, having
fSCLK = 52 MHz and a throughput of 3MSPS, gives a cycle time of
t2 + 12.5(1/fSCLK) + tACQ =
333 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ.
Figure 6 shows that, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a value of TBD
ns for tQUIET satisfying the minimum requirement of TBD ns.
Timing Example 2
Having
fSCLK = 20 MHz and a throughput of 1.5 MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 666 ns.
With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ. From
Figure 6, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a values of TBD ns for
tQUIET satisfying the minimum requirement of TBD ns.
Figure 6. Serial Interface Timing Example
Figures 5 and 6 show some of the timing parameters from the Timing Specifications table.
&6
SCLK
15
13
15
SDATA
2 LEADING
ZERO’S
THREE-
STATE
t4
2
3
4
16
t5
t3
tquiet
tconvert
t 2
THREE-STATE
DB10
t6
t7
t8
14
ZERO
Z
B
t1
1/ THROUGHPUT
DB11
DB9
ZERO
ZERO
DB0
DB1
2 TRAILING
ZERO’S
SCLK
1
5
2
34
&6
13
tquiet
t2
t8
14
B
tacquisition
12.5(1/fSCLK)
1/THROUGHPUT
tconvert
t1
15
16
12


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