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CDCM7005-SP 데이터시트(PDF) 2 Page - Texas Instruments

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부품명 CDCM7005-SP
상세설명  CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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CDCM7005-SP
SGLS390G – JULY 2009 – REVISED NOVEMBER 2015
www.ti.com
Product Folder Links: CDCM7005-SP
Submit Documentation Feedback
Copyright © 2009–2015, Texas Instruments Incorporated
Table of Contents
1
Features .................................................................. 1
2
Applications ........................................................... 1
3
Description ............................................................. 1
4
Revision History..................................................... 2
5
Description (continued)......................................... 4
6
Pin Configuration and Functions ......................... 5
7
Specifications......................................................... 7
7.1
Absolute Maximum Ratings ...................................... 7
7.2
ESD Ratings.............................................................. 7
7.3
Recommended Operating Conditions ....................... 8
7.4
Thermal Information .................................................. 9
7.5
Electrical Characteristics........................................... 9
7.6
Timing Requirements .............................................. 11
7.7
Typical Characteristics ............................................ 12
8
Parameter Measurement Information ................ 14
9
Detailed Description ............................................ 18
9.1
Overview ................................................................. 18
9.2
Functional Block Diagram ....................................... 19
9.3
Feature Description................................................. 20
9.4
Device Functional Modes........................................ 27
9.5
Programming........................................................... 28
10
Application and Implementation........................ 37
10.1
Application Information.......................................... 37
10.2
Typical Application ............................................... 40
11
Power Supply Recommendations ..................... 43
12
Layout................................................................... 43
12.1
Layout Guidelines ................................................. 43
12.2
Layout Examples................................................... 44
13
Device and Documentation Support ................. 45
13.1
Community Resources.......................................... 45
13.2
Trademarks ........................................................... 45
13.3
Electrostatic Discharge Caution ............................ 45
13.4
Glossary ................................................................ 45
14
Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (January 2014) to Revision G
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Deleted two bullets from the Features List. ........................................................................................................................... 1
Changes from Revision E (August 2012) to Revision F
Page
Added /EM bullet to Features ................................................................................................................................................. 1
Deleted Ordering Information table ........................................................................................................................................ 4
Changes from Revision D (December 2011) to Revision E
Page
Changed PLL_LOCK pin description, replaced cycle-slip text. .............................................................................................. 5
Changed the Frequency Hold-Over Mode section ............................................................................................................... 24
Changed text From: Cycle-Slip To: Frequency Offset in Figure 22 ..................................................................................... 26
Changed table Word 3, Cycle Slip (Bit 6) To: Frequency Offset.......................................................................................... 32
Changed Note 1 of table Word 3.......................................................................................................................................... 32
Changed table Lock-Detect Window (Word 3) - Clip slip To: Frequency offset, and Note 2 ............................................... 34
Changes from Revision B (December 2009) to Revision C
Page
Changed the VCC pin text - From: There is no internal connection between VCC and AVCC To: VCC and AVCC should
always have same supply voltage .......................................................................................................................................... 5
Added to the CTRL_LE - Unused or floating inputs must be tied to proper logic level. It is recommended to use a
20-k
Ω or larger pullup resistor to VCC ................................................................................................................................... 6
Added to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. It is recommended to use
a 20-k
Ω or larger pullup resistor to VCC ................................................................................................................................ 6


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