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AD7912ARM 데이터시트(PDF) 4 Page - Analog Devices |
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AD7912ARM 데이터시트(HTML) 4 Page - Analog Devices |
4 / 32 page AD7912/AD7922 Rev. 0 | Page 4 of 32 Parameter A Grade1 Unit Test Conditions/Comments CONVERSION RATE Conversion Time 777 ns max 14 SCLK cycles with SCLK at 18 MHz Track-and-Hold Acquisition Time2 290 ns max Throughput Rate 1 MSPS max POWER REQUIREMENTS VDD 2.35/5.25 V min/max IDD Digital I/Ps = 0 V or VDD Normal Mode (Static) 3 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off 1.5 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off Normal Mode (Operational) 4 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS 2 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS Full Power-Down Mode (Static) 1 µA max SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.48 mA typ VDD = 5 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS 0.26 mA typ VDD = 3 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS Power Dissipation4 Normal Mode (Operational) 20 mW max VDD = 5 V, fSAMPLE = 1 MSPS 6 mW max VDD = 3 V, fSAMPLE = 1 MSPS Full Power-Down 5 µW max VDD = 5 V 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section. |
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