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SM320C6457CGMHS 데이터시트(PDF) 9 Page - Texas Instruments |
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SM320C6457CGMHS 데이터시트(HTML) 9 Page - Texas Instruments |
9 / 209 page 9 SM320C6457-HIREL www.ti.com SPRS948 – JULY 2016 Submit Documentation Feedback Product Folder Links: SM320C6457-HIREL Terminal Configuration and Functions Copyright © 2016, Texas Instruments Incorporated Table 3-2. Pin Attributes (continued) SIGNAL NAME BALL NO. TYPE IPD/IPU DESCRIPTION EMU0(3) AD5 I/O/Z IPU Emulation pin 0 EMU1(3) AE5 Emulation pin 1 EMU2 AH5 Emulation pin 2 EMU3 AE4 Emulation pin 3 EMU4 AH4 Emulation pin 4 EMU5 AG4 Emulation pin 5 EMU6 AF4 Emulation pin 6 EMU7 AG2 Emulation pin 7 EMU8 AG3 Emulation pin 8 EMU9 AD4 Emulation pin 9 EMU10 AE3 Emulation pin 10 EMU11 AF2 Emulation pin 11 EMU12 AE1 Emulation pin 12 EMU13 AF3 Emulation pin 13 EMU14 AC1 Emulation pin 14 EMU15 AD1 Emulation pin 15 EMU16 AD3 Emulation pin 16 EMU17 AA1 Emulation pin 17 EMU18 AC2 Emulation pin 18 RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET AH23 I Device reset NMI AE19 I IPD Nonmaskable interrupt, edge-driven (rising edge). NOTE: Any noise on the NMI pin may trigger an NMI interrupt. Therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded instead of relying on the IPD. RESETSTAT AF23 O Reset Status pin. The RESETSTAT pin indicates when the device is in reset POR AG22 I Power on reset. GP15 F23 I/O/Z IPD General-purpose input/output (GPIO) pins (I/O/Z). GPIO[15:0] pins are multiplexed at power-on reset for configuration latching: • GPIO[0] is mapped to LENDIAN • GPIO[4:1] are mapped to BOOTMODE[3:0] (see Section 5.7) • GPIO[8:5] are mapped to DEVNUM[3:0] • GPIO[13:9] are mapped to CFGGP[4:0] • GPIO[14] is mapped to HPIWIDTH • GPIO[15] is mapped to ECLKINSEL GP14 D23 GP13 C23 GP12 D24 GP11 C25 GP10 A25 GP09 C24 GP08 B25 GP07 F5 GP06 C5 GP05 F6 GP04 B5 GP03 B4 GP02 D5 GP01 E5 GP00 A5 |
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