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SN74HC132 데이터시트(PDF) 10 Page - Texas Instruments

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부품명 SN74HC132
상세설명  Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs
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Vcc
Unused Input
Input
Output
Input
Unused Input
Output
AHC132
HC132
AC132
10
SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
www.ti.com
Product Folder Links: SN54HC132 SN74HC132
Submit Documentation Feedback
Copyright © 1982–2016, Texas Instruments Incorporated
Typical Application (continued)
9.2.3 Application Curve
Figure 6. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply-voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µF is recommended. If there are multiple VCC pins then a 0.01 µF or a 0.022 µF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µF and a
1 µF are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the outputs section of the part when asserted.
This does not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Figure 7. Layout Diagram


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