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SWITCHING CHARACTERISTICS

SN65MLVD128

SN65MLVD129

SLLS586 – MARCH 2004

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

UNIT

Propagation delay time, low-to-high-level output

See Figure 5

1

3

ns

Propagation delay time, high-to-low-level output

1

3

ns

Differential output signal rise time

1

2

ns

Differential output signal fall time

1

2

ns

100

ps

Output skew

160

ps

100

ps

800

ps

100 MHz clock input, All channels enabled

1

3

ps

100 MHz clock input, All channels enabled

20

ps

46

110

ps

enabled

Enable time, high-impedance-to-high-level output

7

ns

See Figure 6

Enable time, high-impedance-to-low-level output

7

ns

Disable time, high-level-to-high-impedance output

7

ns

See Figure 6

Disable time, low-level-to-high-impedance output

7

ns

(1)

All typical values are at 25°C and with a 3.3-V supply voltage.

(2)

bank.

(3)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(4)

Stimulus jitter has been subtracted from the numbers.

5

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