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GQL OR ZQL PACKAGE

(TOP VIEW)

J

H

G

F

E

D

C

B

A

2

1

3

4

6

5

K

A

B

C

D

E

F

G

H

J

K

1

2

3

4

5

6

Y1

Y3

Y5

Y7

Y9

Y10

Y12

Y14

Y16

Y18

NC

Y2

Y4

Y6

Y8

Y11

Y13

Y15

Y17

OE

NC

GND

GND

GND

GND

LE

GND

GND

GND

GND

GND

GND

NC

A2

A4

A6

A8

A11

A13

A15

A17

CLK

A1

A3

A5

A7

A9

A10

A12

A14

A16

A18

(1) NC − No internal connection

OE

CLK

Y1

1D

C1

CLK

To 17 Other Channels

LE

A1

27

30

28

54

3

Pin numbers shown are for the DGG, DGV, and DL packages.

SN74ALVC16834

18-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES140I – JULY 1998 – REVISED OCTOBER 2004

FUNCTION TABLE

INPUTS

OUTPUT

Y

OE

LE

CLK

A

H

X

X

X

Z

L

L

X

L

L

L

L

X

H

H

L

H

↑

L

L

L

H

↑

H

H

L

H

H

X

L

H

L

X

(1)

Output level before the indicated steady-state input conditions were

established, provided that CLK is high before LE goes high

(2)

Output level before the indicated steady-state input conditions were

established

LOGIC DIAGRAM (POSITIVE LOGIC)

2