전자부품 데이터시트 검색엔진 |
|
SN74HC02PWT 데이터시트(PDF) 11 Page - Texas Instruments |
|
|
SN74HC02PWT 데이터시트(HTML) 11 Page - Texas Instruments |
11 / 29 page 0 25 50 75 100 125 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 Supply Voltage (V) C001 11 SN54HC02, SN74HC02 www.ti.com SCLS076F – DECEMBER 1982 – REVISED APRIL 2015 Product Folder Links: SN54HC02 SN74HC02 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated Typical Application (continued) 9.2.3 Application Curve Figure 5. Typical Output Pulse Length Over VCC Range 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1- μF bypass capacitor. If there are multiple VCC pins, TI recommends a 0.01-μF or 0.022-μF bypass capacitors for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. Two bypass capacitors of value 0.1 μF and 1 μF are commonly used in parallel. For best results, install the bypass capacitor(s) as close to the power pin as possible. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Absolute Maximum Ratings are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 11.2 Layout Example Figure 6. Layout Recommendation |
유사한 부품 번호 - SN74HC02PWT |
|
유사한 설명 - SN74HC02PWT |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |