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SN74LV573PWLE 데이터시트(PDF) 1 Page - Texas Instruments

부품명 SN74LV573PWLE
상세설명  OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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SN54LV573, SN74LV573
OCTAL TRANSPARENT DTYPE LATCHES
WITH 3STATE OUTPUTS
SCLS198B − FEBRUARY 1993 − REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
D EPIC  (Enhanced-Performance Implanted
CMOS) 2-
µ Process
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These octal transparent D-type latches are
designed for 2.7-V to 5.5-V VCC operation.
The ’LV573 feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN74LV573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV573 is characterized for operation over the full military temperature range of −55
°C to 125°C. The
SN74LV573 is characterized for operation from −40
°C to 85°C.
Copyright
 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
32 1 20 19
910 11 1213
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18
17
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2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
SN54LV573 . . . FK PACKAGE
(TOP VIEW)
SN54LV573 . . . J OR W PACKAGE
SN74LV573 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
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11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE


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