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TL16PNP550AFNR 데이터시트(PDF) 1 Page - Texas Instruments |
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TL16PNP550AFNR 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 40 page TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUGANDPLAY (PnP) AND AUTOFLOW CONTROL SLLS190B − MARCH 1995 − REVISED MARCH 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 D PnP Card Autoconfiguration Sequence Compliant D External Terminal-to-Bypass PnP Autoconfiguration Sequence D In UART Bypass Mode, the Stand-Alone PnP Controller is Configured With One Logical Device D Provides 10-Interrupts IRQ3−IRQ7, IRQ9 −IRQ12, IRQ15 D Simple 3-Pin Interface to SGS-Thomson EEPROM 2K/4K ST93C56/66 D High Output Current Drive. No External Buffer Needed for Data and Interrupt Signals D Programmable Auto-RTS and Auto-CTS D In Auto-CTS Mode, CTS Controls Transmitter D In Auto-RTS Mode, Receiver FIFO Contents and Threshold Control RTS D The Serial and Modem Control Outputs Drive a 1-Meter RJ11 Cable Directly if Equipment Is on the Same Power Drop D Capable of Running With All Existing TL16C450 Software D After Reset, All Registers Are Identical to the TL16C450 Register Set D Clock Prescalar Allows 22-MHz Oscillator Clock to be Divided by 12, 6, 3, or 1 D In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data D Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 −1) and Generates an Internal 16 × Clock D On-Chip I/O Port Address Decoding D In PnP Bypass Mode, 6 External Terminals Configure the I/O Base Address and Interrupt Mapping D Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream D Independent Control of Transmit, Receive, Line Status, and Data Set Interrupts on Each Channel D Programmable Serial Interface Characteristics: − 5-, 6-, 7-, or 8-Bit Characters − Even-, Odd-, or No-Parity-Bit Generation and Detection − 1-, 1 1/2-, or 2-Stop Bit Generation − Baud Generation (DC to 1 Mbit Per Second) D False Start Bit Detection D Complete Status Reporting Capabilities D 3-State Outputs Provide TTL Drive for Bidirectional Data Bus and Interrupt Lines D Line Break Generation and Detection D Internal Diagnostic Capabilities: − Loopback Controls for Communications Link Fault Isolation − Break, Parity, Overrun, and Framing Error Simulation D Fully Prioritized Interrupt System Controls D Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD) D Transmitter and Receiver Run at the Same Speed D Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation for the Internal ACE D Available in 68-Pin PLCC description The TL16PNP550A is a functional upgrade of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16PNP550A, like the TL16C550C, can be placed in an alternate mode (FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1996, Texas Instruments Incorporated SGS-Thomson is a trademark of SGS-Thomson Incorporated. |
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