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CS5520-BP 데이터시트(PDF) 11 Page - Cirrus Logic |
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CS5520-BP 데이터시트(HTML) 11 Page - Cirrus Logic |
11 / 41 page THEORY OF OPERATION The front page of this data sheet illustrates the block diagram of the CS5516 and CS5520 A/D converter. The device includes an instrumenta- tion amplifier with a fixed gain of 25. This chopper-stabilized instrumentation amplifier is followed by a programmable gain stage with gain settings of 1, 2, 4, and 8. The sensitivity of the input is a function of the programmable gain setting and of the reference voltage connected between the VREF+ and VREF- pins of the de- vice. The full scale of the converter is VREF/( G x 25) in unipolar, or ±VREF/(G x 25) in bipolar, where VREF is the reference voltage between the VREF+ and VREF- pins, G is the gain set- ting of the programmable gain amplifier, and 25 is the gain of the instrumentation amplifier. After the programmable gain block, the output of a 4-bit DAC is combined with the input sig- nal. The DAC can be used to add or subtract offset from the analog input signal. Offsets as large as ±200 % of full scale can be trimmed from the input signal. The CS5516 and CS5520 are optimized to per- form ratiometric measurement of bridge-type transducers. The devices support dc bridge exci- tation or two modes of ac (switched dc) bridge excitation. In the switched-dc modes of opera- tion the converter fully demodulates both the reference voltage and the analog input signal from the bridge. XOUT VD+ VA+ VREF+ VREF- DGND VA- 1 µF AIN+ AIN- MDRV- 0.1 µF SCLK SOD SID SMODE CS5516 CS5520 XIN 0.1 µF 10 Ω 0.1 µF VD- AGND2 MDRV+ DRDY CS 10 Ω +5V Analog Supply -5V Analog Supply 0.1 µF 1 µF1 µF 1 µF 1 µF RST + - 1 2 9 10 6 7 5 8 AGND1 320 23 22 16 18 17 24 15 13 14 19 21 4 Unused logic inputs must be connected to DGND or VD+ Optional Clock Source Control Logic Serial Data Interface Figure 2. System Connection Diagram: DC Excitation Mode (EXC bit = 0), F1 = F0 = 0. CS5516, CS5520 DS74F1 11 DS74F2 11 |
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