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CD74HC597MT 데이터시트(PDF) 2 Page - Texas Instruments |
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CD74HC597MT 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 14 page 2 Functional Diagram 9 1 2 3 4 6 12 7 5 D1 D2 D3 D4 D5 D6 D7 STCP Q7 11 13 10 15 14 D0 DS SHCP PL MR 8 F/F STORAGE REG. 8-BIT SHIFT REG. PARALLEL DATA INPUTS FUNCTION TABLE STCP SHCP PL MR FUNCTION ↑ X X X Data Loaded to Input Flip-Flops ↑ X L H Data Loaded from Inputs to Shift Register No Clock Edge X L H Data Transferred from Input Flip-Flops to Shift Register X X L L Invalid Logic, State of Shift Register Indeterminate when Signals Removed X X H L Shift Register Cleared X ↑ H H Shift Register Clocked Qn = Qn-1, Q0 = DS H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High CP Level CD54HC597, CD74HC597, CD74HCT597 |
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