1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

OUT2P

OUT2N

V

CC

VLIM

SENSE

RMI

VTH

CPWM

FG

RD

OUT1P

OUT1N

VOVER

SGND

6VREG

ROFF

CT

IN+

HB

IN–

TMP814

www.ti.com

SLDS151A – MAY 2009 – REVISED JUNE 2015

5 Pin Configuration and Functions

PW Package

20-Pin TSSOP

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NO.

NAME

1

OUT2P

O

Upper-side driver output

2

OUT2N

O

Lower-side driver output

Power supply. For the CM capacitor that is a power stabilization capacitor for PWM drive and for

absorption of kickback, the capacitance of 0.1

μF to 1 μF is used. In this device, the lower TR

3

VCC

with the thick pattern and along the shortest route. Use a zener diode if kickback causes

excessive increase of the supply voltage, because such increase may damage the device.

Activates the current limiter when SENSE voltage is greater than VLIM voltage. Connect to

4

VLIM

I

6VREG when not used.

5

SENSE

I

Sense input. Connect to GND when not used.

Minimum speed setting. Connect to 6VREG when not used. If device power can be removed

6

RMI

I

before power is removed from RMI, insert a current limiting resistor to prevent inflow of large

current.

7

VTH

I

VTH : Connect to GND if not used (Full Speed).

Connect to capacitor CP to set the PWM oscillation frequency. With CP = 100 pF, oscillation

8

CPWM

O

occurs at 25 kHz and provides the basic frequency of PWM.

Open collector output, which can detect the rotation speed using the FG output according to the

9

FG

O

phase shift. Leave open when not used.

10

RD

O

Open collector output. Outputs low during rotation and high at stop. Leave open when not used.

11

IN–

I

Hall input

12

HB

O

This is a Hall element bias, that is, the 1.5-V constant-voltage output.

Hall input. Make connecting traces as short as possible to prevent carrying of noise. To futher

limit noise, insert a capacitor between IN+ and IN–. The Hall input circuit is a comparator having

13

IN+

I

a hysteresis of 20 mV. The application should ensure that the Hall input level more than three

times (60 mVp-p) this hysteresis.

14

CT

O

Lock detection time setting. Capacitor CT is connected.

Sets the soft switching time to cut the reactive current before phase change. Connect to 6VREG

15

ROFF

I

when not used.

16

6VREG

O

6-V regulator output

17

SGND

Connected to the control circuit power supply system.

Constant-voltage bias and should be used for application of 24 V and 48 V (see Figure 7). A

18

VOVER

O

current limiting resistor should be used. Leave open when not used.

19

OUT1N

O

Lower-side driver output

20

OUT1P

O

Upper-side driver output

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