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SMJ3C6414C 데이터시트(PDF) 5 Page - Texas Instruments |
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SMJ3C6414C 데이터시트(HTML) 5 Page - Texas Instruments |
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5 / 133 page  SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device characteristics Table 1 provides an overview of the C6414, C6415, and C6416 DSPs. The table shows significant features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1. Characteristics of the C6414, C6415, and C6416 Processors HARDWARE FEATURES C6414, C6415, AND C6416 EMIFA (64-bit bus width) (default clock source = AECLKIN) 1 Peripherals EMIFB (16-bit bus width) (default clock source = BECLKIN) 1 Peripherals Not all peripherals pins EDMA (64 independent channels) 1 Not all peripherals pins are available at the same HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32) are available at the same time. (For more details, see the Device PCI (32-bit) [DeviceID Register value 0xA106] 1 [C6415/C6416 only] time. (For more details, see the Device Configuration section.) Peripheral performance is McBSPs (default internal clock source = CPU/4 clock frequency) 3 Peripheral performance is dependent on chip-level UTOPIA (8-bit mode) 1 [C6415/C6416 only] dependent on chip-level configuration. 32-Bit Timers (default internal clock source = CPU/8 clock frequency) 3 General-Purpose Input/Output 0 (GP0) 16 Decoder Coprocessors VCP 1 (C6416 only) Decoder Coprocessors TCP 1 (C6416 only) Size (Bytes) 1056K On-Chip Memory Organization 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 1024KB Unified Mapped RAM/Cache (L2) CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01 Device_ID Silicon Revision Identification Register (DEVICE_REV [19:16]) Address: 0x01B0 0200 DEVICE_REV[19:16] Silicon Revision 1111 1.03 or earlier 0001 1.03 0010 or 0000 1.1 Frequency MHz 600 Cycle Time ns 1.67 ns (C6414, C6415, C6416) and (C6414A, C6415A, C6416A) [600-MHz CPU, 133-MHz EMIFA]† Voltage Core (V) 1.4 V Voltage I/O (V) 3.3 V PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12 PGA Package 33 x 33 mm 570-Pin PGA (GAD) Process Technology µm 0.13 µm Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) PD † On these C64x devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the EMIF Device Speed section of this data sheet. |
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