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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TPS546C20A 데이터시트(PDF) 3 Page - Texas Instruments |
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TPS546C20A 데이터시트(HTML) 3 Page - Texas Instruments |
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3 / 97 page  Thermal Pad 1 RT 2 VSEL 3 SS 4 PMB_DATA 5 PMB_CLK 6 SMB_ALRT 7 BOOT 8 SW 9 SW 10 SW 11 SW 12 SW 21 PVIN 22 PVIN 23 PVIN 24 PVIN 25 PVIN 26 DRGND 27 BP3 28 BP6 29 AVIN 30 RESET/PGD 31 ISHARE 32 VSHARE Not to scale 3 TPS546C20A www.ti.com SLUSCK1A – JULY 2016 – REVISED AUGUST 2016 Product Folder Links: TPS546C20A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 5 Pin Configuration and Functions RVF Package 40-Pin LQFN With Exposed Thermal Pad Top View Pin Functions PIN I/O DESCRIPTION NAME NO. AGND 38 — Analog ground return for controller device. Connect this pin to PGND and DRGND at the thermal pad. AVIN 29 I Input power to the controller. Connect a low-impedance bypass with a minimum of 1 µF to PGND. The AVIN voltage is also used for input feed-forward. PVIN and AVIN must be the same potential for accurate short circuit protection. BP3 27 O Output of the 3.3-V onboard regulator. This regulator powers the controller and should be bypassed with a minimum of 2.2 µF to AGND. The BP3 pin is not designed to power external circuit. BP6 28 O Output of the 6.5-V onboard regulator. This regulator powers the driver stage of the controller and should be bypassed with a minimum of 2.2 µF to the thermal pad (power-stage ground, essentially PGND). TI recommends using an additional 100-nF (typical) bypass capacitor for reducing ripple on BP6. The low- impedance bypassing of this pin to PGND is critical. BOOT 7 I/O Bootstrap pin for the internal flying high-side driver. Connect a 100-nF (typical) capacitor from this pin to the SW pin. To reduce the voltage spike at SW, a BOOT resistor with a value between 1 Ω to 15 Ω can be placed in series with the BOOT capacitor to slow down turnon of the high-side FET. CNTL 40 I PMBus CNTL pin. See the Supported PMBus Commands section. The CNTL pin has an internal pullup and floats high when left floating. COMP 37 O Output of the error amplifier. Connect compensator network from this pin to the FB pin. DIFFO 35 O Output of the differential remote sense amplifier. This provides remote sensing for output voltage reporting and the voltage control loop. For the loop slave device in a 2-phase configuration, the DIFFO pin can be left floating. DRGND 26 — Power ground return for controller device. This pin should be directly connected to the thermal pad on the PCB board. FB 36 I Feedback pin for the control loop. Negative input of the error amplifier. In 2-phase configuration, the FB pin of the loop slave device should be tied to the BP3 pin. |
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