전자부품 데이터시트 검색엔진 |
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SI5347 데이터시트(PDF) 1 Page - Silicon Laboratories |
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SI5347 데이터시트(HTML) 1 Page - Silicon Laboratories |
1 / 55 page Si5347/46 Rev D Data Sheet Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators The Si5347 is a high-performance, jitter-attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and inde- pendent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on 4th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5347/46 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up in a known configuration. Programming the Si5347/46 is easy with Silicon Labs' ClockBuilder Pro software. Factory pre-programmed devices are also available. Applications • OTN Muxponders and Transponders • 10/40/100G network line cards • GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262) • Carrier Ethernet switches • Broadcast video KEY FEATURES • Four or two independent DSPLLs, any output frequency from any input frequency • Ultra-low jitter of 95 fs rms • Input frequency range: • External Crystal: 25–54 MHz • Differential: 8 kHz to 750 MHz • LVCMOS: 8 kHz to 250 MHz • Output frequency range: • Differential: up to 712.5 MHz • LVCMOS: up to 250 MHz • Status Monitoring • Hitless switching • Si5347: 4 input, 8 output, 64-QFN 9×9 mm • Si5346: 4 input, 4 output, 44-QFN 7×7 mm OUT7 OUT6 OUT5 OUT1 OUT4 OUT3 OUT2 OUT0 I2C / SPI Control NVM Status Flags Status Monitor XB XA 25-54 MHz XTAL OSC ÷FRAC DSPLL D DSPLL C DSPLL B DSPLL A ÷FRAC ÷FRAC ÷FRAC ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT 4 Input Clocks IN0 IN1 IN2 IN3 silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 |
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