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SI5380 데이터시트(PDF) 1 Page - Silicon Laboratories |
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SI5380 데이터시트(HTML) 1 Page - Silicon Laboratories |
1 / 53 page Si5380 Rev D Data Sheet Ultra-Low Phase Noise, 12-output JESD204B Clock Generator The Si5380 is a high performance, integer-based (M/N) clock generator for small cell applications which demand the highest level of integration and phase noise perform- ance. Based on Silicon Laboratories’ 4th generation DSPLL™ technology, the Si5380 combines frequency synthesis and jitter attenuation in a highly integrated digital solu- tion that eliminates the need for external VCXO and loop filter components. A low-cost, fixed-frequency crystal provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. Applications: • JESD204B clock generation • Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells • Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A) • Remote Radio Head (RRH), wireless repeaters, wireless backhaul • Data conversion sampling clocks (ADC, DAC, DDC, DUC) KEY FEATURES • DSPLL eliminates external VCXO and analog loop filter components • Supports JESD204B clocking: DCLK and SYSREF • Ultra-low jitter of 65 fs • Input frequency range: • External Crystal: 54 MHz • Differential: 11.52 MHz to 737.28 MHz • LVCMOS: 11.52 MHz to 245.76 MHz • Output frequency range: • Differential: 480 kHz to 1.47456 GHz • LVCMOS: 480 kHz to 245.76 MHz • Status monitoring • Hitless switching • Si5380: 4 input, 12 output, 64-QFN 9×9 mm Device and System Clocks Si5380 I2C / SPI Control NVM Status Flags Status Monitor XB XA 54 MHz XTAL OSC ÷INT ÷INT ÷INT DSPLL ÷INT 4 Input Clocks IN0 IN1 IN2 IN3/FB_IN OUT6 OUT5 OUT4 OUT0 OUT3 OUT2 OUT1 OUT0A ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT OUT8 OUT7 ÷INT ÷INT OUT9A OUT9 ÷INT ÷INT Delay Delay Delay Delay Delay silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 |
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