GS82583ED18/36GK-675/625/550/500

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.05 8/2016

9/26

© 2014, GSI Technology

Driver Impedance Control

Programmable Driver Impedance is implemented on the following output signals:

• CQ, CQ, Q, QVLD.

Driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST

is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.

Output Signal

CQ, CQ, Q, QVLD

RQ*0.2

 15%

RQ*0.2

 15%

Notes:

ODT Impedance Control

Programmable ODT Impedance is implemented on the following input signals:

• CK, CK, KD, KD, SA, R, W, D.

ODT impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST

is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system

Input Signal

PZT[1:0]

MZT[1:0]

CK, CK, KD, KD

X0

XX

disabled

disabled

X1

01

RT

 15%

RT

 15%

10

RT*2

 20%

RT*2

 20%

SA, R, W

0X

XX

disabled

disabled

1X

01

RT

 15%

RT

 15%

10

RT*2

 20%

RT*2

 20%

D

XX

01

RT

 15%

RT

 15%

10

RT*2

 20%

RT*2

 20%

Notes:

1. When MZT[1:0] = 00, ODT is disabled on all inputs. MZT[1:0] = 11 is reserved for future use.

4. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions.

Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be

diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would.

This could result in the device’s operating currents being higher.