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SL2101CNP2Q 데이터시트(PDF) 6 Page - Zarlink Semiconductor Inc |
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SL2101CNP2Q 데이터시트(HTML) 6 Page - Zarlink Semiconductor Inc |
6 / 27 page SL2101 Data Sheet 6 Zarlink Semiconductor Inc. Programmable Features Synthesizer programmable divider Function as described above Reference programmable divider Function as described above. Charge pump current The charge pump current can be programmed by bits C1 & C0 within data byte 4, as defined in Figure 29. Power setting The device power and hence signal handling can be programmed by bits I2 - I0 within data byte 5, as defined in Figure 7. In all power settings the synthesizer remains enabled to facilitate rapid PLL lock reacquisition Test mode The test modes are defined by bits T2 - T0 as described in Figure 26. General purpose ports, P0 The general purpose port can be programmed by bits P0; Logic '1' = on Logic '0' = off (high impedance) - this is the default state at device power on Buffered crystal reference output, BUFREFThe buffered crystal reference frequency can be switched to the BUFREF output by bit RE as described in Figure 27. The BUFREF output defaults to the 'ON' condition at device power up. This output is only available on the SSOP package. Figure 4 - Nominal Output Load as Upconverter into Differential SAWF 15 14 10nH 10nH Vcc SL2101 OUTPUT OUTPUTB 200 Ω 200 Ω SAWF 33 Ω 33 Ω |
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