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SLE88CL1M52P 데이터시트(PDF) 8 Page - Infineon Technologies AG |
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SLE88CL1M52P 데이터시트(HTML) 8 Page - Infineon Technologies AG |
8 / 9 page SLE 88CF4000P Short Product Information 8 / 9 12.2009 The SLE 88 Family fully meets the requirements for real multi-application operating systems. The advanced 0.13µm technology, the Integral Security Concept, the low power optimised 32-bit core supported by various powerful peripherals, and the possibility to adapt the performance to application requirements establish the foundation for a completely new chip card generation. The High Performance is ensured by the 32-bit RISC architecture that processes instructions and data 32-bit wise supplied by 2 dedicated caches. A very efficient context/application switching mechanism allows fast switching between multiple tasks. An Integral Security Concept, based on the entire integration of security measures at each hardware and software design phase, has been used for the development of the SLE 88 Family. An Interrupt Control Unit supports a programmable interrupt system with UART, timers, and the other peripherals as interrupt sources. A variety of different Trap Vectors informs the operating system about exceptions (e.g. access violation). The architecture allows the Linear Addressing of Large Memories for a more convenient code implementation. The Memory Management and Protection Unit (MMU) handles a virtual address range of 4 Gbytes, and serves as a hardware firewall to enable secure separation of adjacent application codes and data. Program and data modules are organised as packages. Each package has a defined memory range of 16 Mbytes with dedicated access rights for memories and peripherals. With the 0.13µm process, the SLE 88 Family offers large on-chip memories (ROM, EEPROM, RAM). The EEPROM space is the basis of Infineon Technologies “Flash” Concept where the entire EEPROM is freely configurable in code and data sections, and so can be used to store an Operating System, as well as application code and data. This customization provides added value to the system and the possibility to serve multiple projects with the same platform. This concept offers the flexibility and convenience of Flash memory, but takes advantage of the EEPROM cell quality (timing, cycling and endurance). A number of powerful peripherals offer hardware support for time and code intensive operations. : • DES Accelerator for symmetric crypto operations based on DES and Triple DES • True Random Number Generator (TRNG) to supply the CPU with true random numbers whose quality is tested according to AIS-31 strict evaluation guidelines • Intelligent Power Manager which automatically adjusts the internal frequency accordingly to the power classes A,B,C • Three 16-bit timers for protocol implementation, event monitoring, etc… |
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