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UCD3138A 데이터시트(PDF) 63 Page - Texas Instruments |
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UCD3138A 데이터시트(HTML) 63 Page - Texas Instruments |
63 / 87 page 2 B – QB2 ( EDGEGEN ) 2 A – QT 2 ( EDGEGEN ) 0B – QSYN 2,4 1 B – QSYN 1,3 X3 X2 DPWM 2 AF DPWM 2 BF DPWM 3 AF DPWM 3 BF Current X1 Peak Level 3 A – QB1 ( DPWM 1 C) 3 B – QT1 ( DPWM 2 C) Period Start Period End 1A 0A Chopping point Chopping point Y3 Y2 Y 1 63 UCD3138A www.ti.com SLUSC66C – MARCH 2015 – REVISED SEPTEMBER 2016 Submit Documentation Feedback Product Folder Links: UCD3138A Application and Implementation Copyright © 2015–2016, Texas Instruments Incorporated X 1 , X 2 , X 3 and Y 1 , Y 2 , Y 3 are sets of moving edges. All other edges are fixed Figure 8-11. Dynamic Signals to Bridge The Edge Generator is configured with these statements: Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE = 2; Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE = 5; Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE = 6; Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE = 1; Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 1; // EDGEGEN-A out the A output Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 1; // EDGEGEN-B out the B output Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN = 1; The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing delay through the DPWM. The finial 6 gate signals are shown in Figure 8-12. |
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