전자부품 데이터시트 검색엔진 |
|
TSC2100IRHBR 데이터시트(PDF) 11 Page - Texas Instruments |
|
|
TSC2100IRHBR 데이터시트(HTML) 11 Page - Texas Instruments |
11 / 77 page TSC2100 SLAS378− NOVEMBER 2003 www.ti.com 11 LRCK/ADWS BCLK DOUT DIN tL(BCLK) ts (DI) th (DI) tS (WS) tH(BCLK) td(DO−BCLK) th(WS) tP(BCLK) th(WS) tS (WS) Figure 4. DSP Timing in Slave Mode TYPICAL TIMING REQUIREMENTS (FIGURE 4) All specifications at 25°C, DVDD = 1.8 V (1) PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER MIN MAX MIN MAX UNITS tH (BCLK) BCLK high period 35 35 ns tL (BCLK) BCLK low period 35 35 ns ts(WS) ADWS/LRCK setup 6 6 ns th(WS) ADWS/LRCK hold 6 6 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns tr Rise time 5 4 ns tf Fall time 5 4 ns (1) These parameters are based on characterization and are not tested in production. |
유사한 부품 번호 - TSC2100IRHBR |
|
유사한 설명 - TSC2100IRHBR |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |