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ST16C552CJ68 데이터시트(PDF) 10 Page - Exar Corporation |
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ST16C552CJ68 데이터시트(HTML) 10 Page - Exar Corporation |
10 / 39 page 10 ST16C552/552A Rev. 3.40 Table 4, INTERNAL REGISTER DECODE A2 A1 A0 READMODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1* 0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register 1 0 0 Modem Control Register 1 0 1 Line Status Register 1 1 0 Modem Status Register 1 1 1 Scratchpad Register Scratchpad Register Baud Rate Register Set (DLL/DLM): Note *2 0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch Printer Port Set (PR/SR/IOSEL/COM/CON): Note *3 X 0 0 PORT REGISTER PORT REGISTER X 0 1 STATUS REGISTER I/O SELECT REGISTER X 1 0 COMMAND REGISTER CONTROLREGISTER Note 1* The General Register set is accessible only when CS A or CS B is a logic 0. Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1. Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the interface signal BIDEN and Printer Control Register bit-5 or IOSEL register. |
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