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73K224L-IP 데이터시트(PDF) 11 Page - TDK Electronics |
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73K224L-IP 데이터시트(HTML) 11 Page - TDK Electronics |
11 / 32 page 73K224L V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem 11 DETECT REGISTER (continued) D7 D6 D5 D4 D3 D2 D1 D0 DR 010 RECEIVE LEVEL INDICATOR S1 PATTERN DETECT RECEIVE DATA UNSCR. MARK DETECT CARR. DETECT ANSWER TONE DETECT CALL PROG. SIGNAL QUALITY INDICATOR BIT NO. NAME CONDITION DESCRIPTION 0 No answer tone detected. D2 Answer Tone Received 1 In Call Init mode, indicates detection of 2225 Hz answer tone in Bell mode (TR bit D0=0) or 2100 Hz if in CCITT mode (TR bit D0=1). The device must be in originate mode for detection of answer tone. Both answer tones are detected in demod mode. 0 No carrier detected in the receive channel. D3 Carrier Detect 1 Indicated carrier has been detected in the received channel. 0 No unscrambled mark. D4 Unscrambled Mark Detect 1 Indicates detection of unscrambled marks in the received data. Should be time qualified by software. D5 Receive Data Continuously outputs the received data stream. This data is the same as that output on the RXD pin, but it is not disabled when RXD is tri-stated. 0 No S1 pattern being received. D6 S1 Pattern Detect 1 S1 pattern detected. Should be time qualified by software. S1 pattern is defined as a double di-bit (001100..) unscrambled 1200 bit/s DPSK signal. Pattern must be aligned with baud clock to be detected. 0 Received signal level below threshold, (typical ≈ -25 dBm0); can use receive gain boost (+18 dB). D7 Receive Level Indicator 1 Received signal above threshold. TONE REGISTER D7 D6 D5 D4 D3 D2 D1 D0 TR 011 RXD OUTPUT CONTR. TRANSMIT GUARD TONE TRANSMIT ANSWER TONE TRANSMIT DTMF DTMF 3 DTMF 2 DTMF 1/ EXTENDED OVER- SPEED DTMF 0/ ANSWER/ GUARD BIT NO. NAME CONDITION DESCRIPTION D6 D5 D4 D0 D0 interacts with bits D6, D5, and D4 as shown. X X 1 X Transmit DTMF tones. X 1 0 0 Select Bell mode answer tone. Interacts with DR bit D2 and TR bit D5. D0 DTMF 0/ Answer/ Guard Tone X 1 0 1 Select CCITT mode answer tone. Interacts with DR bit D2 and TR bit D5. |
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