© 2011 Microchip Technology Inc.

DS21743B-page 5

TC72

FIGURE 1-1:

Serial Port Timing Diagrams.

CE

D7

D0

HIGH Z

SDI

SPI READ DATA TRANSFER

CE

A7 = 1

D7

D0

SDI

A0

A7

A0

t

F

t

R

t

R

SCK

(CP = 0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7 = 0)

(CP = 0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7 = 1)

SDO

SCK

HIGH Z

Note:

The timing diagram is drawn with CP = 0. The

however, the edges of SCK are reversed as defined in Table 4-3 and Figure 4-2.

SPI WRITE DATA TRANSFER

MSb

LSb

MSb

LSb

MSb

LSb

MSb

LSb