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MC10E431 데이터시트(PDF) 1 Page - ON Semiconductor |
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MC10E431 데이터시트(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 11 1 Publication Order Number: MC10E431/D MC10E431, MC100E431 5 V ECL 3‐Bit Differential Flip‐Flop Description The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output. The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge, without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset). The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below VCC. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. Features • Edge-Triggered Asynchronous Set and Reset • Differential D, CLK and Q; VBB Reference Available • 1100 MHz Min. Toggle Frequency • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input 50 kW Pulldown Resistors • ESD Protection: ♦ > 2 kV Human Body Model ♦ > 200 V Machine Model ♦ > 2 kV Charged Device Model • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity: Level 3 (Pb-Free) (For Additional Information, see Application Note AND8003/D) • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 348 Devices • These Devices are Pb-Free, Halogen Free and are RoHS Compliant MARKING DIAGRAM* xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package PLCC−28 FN SUFFIX CASE 776−02 www.onsemi.com *For additional marking information, refer to Application Note AND8002/D. MCxxxE431FNG AWLYYWW 128 MC10E431FNG PLCC−28 (Pb-Free) 37 Units / Tube MC10E431FNR2G 500 Tape & Reel PLCC−28 (Pb-Free) †For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ORDERING INFORMATION Device Package Shipping† MC100E431FNR2G PLCC−28 (Pb-Free) 500 Tape & Reel |
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