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MC100EP31DTG 데이터시트(PDF) 2 Page - ON Semiconductor

부품명 MC100EP31DTG
상세설명  ECL D Flip?륡lop with Set and Reset
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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MC10EP31, MC100EP31
www.onsemi.com
2
1
2
3
45
6
7
8
Q
VEE
VCC
Figure 1. 8-Lead Pinout (Top View) and
Logic Diagram
D
Q
CLK
RESET
SET
S
D
R
Flip Flop
Table 1. PIN DESCRIPTION
Pin
Function
CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
Set*
ECL Asynchronous Set
D*
ECL Data Input
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most neg-
ative supply (GND) or leave unconnec-
ted, floating open.
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
D
SET
RESET
CLK
Q
L
H
X
X
X
L
L
H
L
H
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
UNDEF
Z = LOW to HIGH Transition
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb-Free Pkg
SOIC−8 NB
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
75 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.


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