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DLP9000BFLS 데이터시트(PDF) 8 Page - Texas Instruments

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부품명 DLP9000BFLS
상세설명  Family of 0.9 WQXGA Type A DMDs
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

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DLP9000
DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016
www.ti.com
Product Folder Links: DLP9000
Submit Documentation Feedback
Copyright © 2014–2016, Texas Instruments Incorporated
Pin Functions (continued)
PIN (1)
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
DESCRIPTION
TRACE
(mils) (4)
NAME
NO.
CLOCKS
DCLK_AN
H2
Input
LVDS
Differential
Clock, Negative
740
DCLK_BN
AJ5
Input
LVDS
Differential
Clock, Negative
740
DCLK_CN
C23
Input
LVDS
Differential
Clock, Negative
736
DCLK_DN
AH22
Input
LVDS
Differential
Clock, Negative
736
DCLK_AP
H4
Input
LVDS
Differential
Clock, Positive
740
DCLK_BP
AJ3
Input
LVDS
Differential
Clock, Positive
740
DCLK_CP
C21
Input
LVDS
Differential
Clock, Positive
736
DCLK_DP
AH20
Input
LVDS
Differential
Clock, Positive
738
SERIAL COMMUNICATIONS PORT (SCP)
SCP_DO
AC3
Output
LVCMOS
SDR
Serial Communications Port Output
SCP_DI
AD2
Input
LVCMOS
SDR
Pull-Down
Serial Communications Port Data Input
SCP_CLK
AE1
Input
LVCMOS
Pull-Down
Serial Communications Port Clock
SCP_ENZ
AD4
Input
LVCMOS
Pull-Down
Active-low Serial Communications Port
Enable
MICROMIRROR RESET CONTROL
RESET_ADDR(0)
H12
Input
LVCMOS
Pull-Down
Reset Driver Address Select
RESET_ADDR(1)
C5
Input
LVCMOS
Pull-Down
Reset Driver Address Select
RESET_ADDR(2)
B6
Input
LVCMOS
Pull-Down
Reset Driver Address Select
RESET_ADDR(3)
A19
Input
LVCMOS
Pull-Down
Reset Driver Address Select
RESET_MODE(0)
J1
Input
LVCMOS
Pull-Down
Reset Driver Mode Select
RESET_MODE(1)
G1
Input
LVCMOS
Pull-Down
Reset Driver Mode Select
RESET_SEL(0)
AK4
Input
LVCMOS
Pull-Down
Reset Driver Level Select
RESET_SEL(1)
AL13
Input
LVCMOS
Pull-Down
Reset Driver Level Select
RESET_STROBE
H6
Input
LVCMOS
Pull-Down
Reset Address, Mode, & Level latched on
rising-edge
ENABLES AND INTERRUPTS
PWRDNZ
B4
Input
LVCMOS
Active-low Device Reset
RESET_OEZ
AK24
Input
LVCMOS
Pull-Down
Active-low output enable for DMD reset
driver circuits
RESETZ
AL19
Input
LVCMOS
Pull-Down
Active-low sets Reset circuits in known
VOFFSET state
RESET_IRQZ
C3
Output
LVCMOS
Active-low, output interrupt to ASIC
VOLTAGE REGULATOR MONITORING
PG_BIAS
J19
Input
LVCMOS
Pull-Up
Active-low fault from external VBIAS
regulator
PG_OFFSET
A13
Input
LVCMOS
Pull-Up
Active-low fault from external VOFFSET
regulator
PG_RESET
AC19
Input
LVCMOS
Pull-Up
Active-low fault from external VRESET
regulator
EN_BIAS
J15
Output
LVCMOS
Active-high enable for external VBIAS
regulator
EN_OFFSET
H30
Output
LVCMOS
Active-high enable for external VOFFSET
regulator
EN_RESET
J17
Output
LVCMOS
Active-high enable for external VRESET
regulator
LEAVE PIN UNCONNECTED
MBRST(0)
L5
Output
Analog
Pull-Down
For proper DMD operation, do not connect
MBRST(1)
M28
Output
Analog
Pull-Down
For proper DMD operation, do not connect
MBRST(2)
P4
Output
Analog
Pull-Down
For proper DMD operation, do not connect
MBRST(3)
P30
Output
Analog
Pull-Down
For proper DMD operation, do not connect
MBRST(4)
L3
Output
Analog
Pull-Down
For proper DMD operation, do not connect
MBRST(5)
P28
Output
Analog
Pull-Down
For proper DMD operation, do not connect
MBRST(6)
P2
Output
Analog
Pull-Down
For proper DMD operation, do not connect


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