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LM1851M 데이터시트(PDF) 5 Page - National Semiconductor (TI) |
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LM1851M 데이터시트(HTML) 5 Page - National Semiconductor (TI) |
5 / 8 page Application Circuits A typical ground fault interrupter circuit is shown in Figure 2 It is designed to operate on 120 VAC line voltage with 5 mA normal fault sensitivity A full-wave rectifier bridge and a 15k2W resistor are used to supply the DC power required by the IC A 1 mF capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle When a fault causes the SCR to trigger the circuit breaker is energized and line voltage is removed from the load At this time no fault current flows and the IC discharge current increases from ITH to 3ITH (see Circuit Description and Block Diagram) This quickly resets both the timing capacitor and the output latch At this time the circuit breaker can be reset and the line voltage again sup- plied to the load assuming the fault has been removed A 10001 sense transformer is used to detect the normal fault The fault current which is basically the difference current between the hot and neutral lines is stepped down by 1000 and fed into the input pins of the operational amplifier through a 10 mF capacitor The 00033 mF capacitor be- tween pin 2 and pin 3 and the 200 pF between pins 3 and 4 are added to obtain better noise immunity The normal fault sensitivity is determined by the timing capacitor discharging current ITH ITH can be calculated by ITHe 7V RSET d 2 (1) At the decision point the average fault current just equals the threshold current ITH ITHe If(rms) 2 c 091 (2) where If(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that If charges the timing capacitor only during one half-cycle while ITH dis- charges the capacitor continuously The factor 091 con- verts the rms value to an average value Combining equa- tions (1) and (2) we have RSETe 7V If(rms)c091 (3) For example to obtain 5 mA(rms) sensitivity for the circuit in Figure 2 we have RSETe 7V 5mAc091 1000 e 15M X (4) The correct value for RSET can also be determined from the characteristic curve that plots equation (3) Note that this is an approximate calculation the exact value of RSET de- pends on the specific sense transformer used and LM1851 tolerances Inasmuch as UL943 specifies a sensitivity ‘‘win- dow’’ of 4 mA – 6 mA provision should be made to adjust RSET on a per-product basis Independent of setting sensitivity the desired integration time can be obtained through proper selection of the timing capacitor Ct Due to the large number of variables involved proper selection of Ct is best done empirically The following design example then should only be used as a guideline Assume the goal is to meet UL943 timing requirements Also assume that worst case timing occurs during GF1 start-up (S1 closure) with both a heavy normal fault and a 2X grounded neutral fault present This situation is shown dia- gramatically below TLH5177 – 5 UL943 specifies s25 ms average trip time under these con- ditions Calculation of Ct based upon charging currents due to normal fault only is as follows s 25 ms Specification b 3 ms GFI turn-on time (15k and 1 mF) b 8 ms Potential loss of one half-cycle due to fault current sense of half-cycles only b 4 ms Time required to open a sluggish circuit breaker s 10 ms Maximum integration time that could be allowed 8 ms Value of integration time that accommodates com- ponent tolerances and other variables Ct e I c T V (5) where T e integration time V e threshold voltage I e average fault current into Ct I e 120VAC(rms) RB J c RN RG a RN J X YX Y heavy fault portion of current generated fault current (swamps ITH) shunted around GFI c 1turn 1000 turns J c 12J c (091) (6) X YX YX Y current Ct charging rms to division of on half- average input sense cycles only conversion transformer therefore Cte 120 500 J c 04 16a04 J c 11000J c 12Jc(091)( c00008 175 (7) Cte 001 mF 5 |
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