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TSB41AB3IPFPEP 데이터시트(PDF) 3 Page - Texas Instruments |
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TSB41AB3IPFPEP 데이터시트(HTML) 3 Page - Texas Instruments |
3 / 55 page TSB41AB3EP IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER SGLS122C − JULY 2002 − REVISED JUNE 2008 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k Ω and 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.34 k Ω ±1%. When the power supply of the TSB41AB3 is off while the twisted-pair cables are connected, the TSB41AB3 transmitter and receiver circuitry presents a high-impedance signal to the cable and does not load the TPBIAS voltage at the other end of the cable. When the TSB41AB3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB− terminals can be tied together and then pulled to ground through a 1-k Ω resistor, or the TPB+ and TPB− terminals can be connected to the suggested termination network. The TPA+ and TPA− terminals of an unused port can be left unconnected. The TPBias terminal can be connected to a 1- µF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, it is recommended that the TESTM terminal be connected to VDD through a 1-kΩ resistor, and SE be tied to ground through a 1-k Ω resistor, while SM is connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet and are tied high through a 1-k Ω resistor or hardwired low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender either isochronous resource manager (IRM) or for bus manager (BM). The TSB41AB3 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power conservation state (suspended state) while maintaining a port-to-port connection between 1394 bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all three ports of the TSB41AB3 are suspended, all circuits except the band gap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the 1394a-2000 specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) terminal provides a high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended) and can be used along with LPS to determine when to power down the TSB41AB3. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB3 internal logic. The link power status (LPS) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). |
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