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MC100EP16VCDTG 데이터시트(PDF) 2 Page - ON Semiconductor |
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MC100EP16VCDTG 데이터시트(HTML) 2 Page - ON Semiconductor |
2 / 10 page MC100EP16VC www.onsemi.com 2 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram 1 2 3 45 6 7 8 QHG VEE VCC D QHG EN VBB/D Q VBB D LEN Q LATCH OE Table 1. PIN DESCRIPTION Pin Function D* ECL Data Input Q ECL Data Output QHG, QHG ECL High Gain Data Outputs EN* ECL Enable Input VBB/D Reference Voltage Output / ECL Data Input VCC Positive Supply VEE Negative Supply EP (DFN−8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Elec- trically connect to the most negative supply (GND) or leave unconnected, floating open. *Pins will default LOW when left open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8NB TSSOP−8 DFN−8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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