DRAM

SMJ44400

Austin Semiconductor, Inc.

SMJ44400

Rev. 2.0 10/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

(continued)

Enhanced Paga Mode (continued)

falling edge of RAS\. The buffers act as transparent or flow-

through latches while CAS\ is high. The falling edge of CAS\

latches the column addresses. This feature allows the

SMJ44400 to operate at a higher data bandwidth then conven-

tional page-mode parts, since data retrieval begins as soon as

column address is valid rather than when CAS\ goes low. This

performance improvement is referred to as enhanced page

mode. Valid column address can be presented immediately

after row address hold time has been satisfied, usually well in

advance of the maximum (access time from column address)

has been satisfied. In the event that column addresses for the

next cycle are valid at the time CAS\ goes high, access time

for the next cycle is determined by the later occurrence of

t

CAC

or t

CPA

(access time form rising edge of CAS\).

Address (A0-A9)

Twenty address bits are required to decode 1 of 1,048,576

storage cell locations. Ten row-address bits are set up on

inputs A0 through A9 and latched onto the chip by RAS\. The

ten column-address bits are set up on pins A0 through A9 and

latched onto the chip by CAS\. All addresses must be stable

on or before the falling edges of RAS\ and CAS\. RAS\ is

similar to a chip enable in that it activates the sense

amplifiers as well as the row decoder. CAS\ is used as a chip

select, activating the output buffer as well as latching the

address bits into the column-address buffer.

Write Enable (W\)

The read or write mode is selected through W\. A logic

high on the W\ input selects the read mode and a logic low

selects the write mode. The write-enable terminal can be

driven from standard TTL circuits without a pullup resistor.

The data input is disabled when the read mode is selected.

When W\ goes low prior to CAS\ (early write), data out

reamins in the high-impedance state for the entire cycle

permitting a write operation independent of the state of OE\.

This permits early-write operation to be completed with OE\

grounded.

Data In/Out (DQ1 - DQ4)

The high-impedance output buffer provides direct TTL

compatibility (no pullup resistor required) with a fanout of

two Series 54 TTL loads. Data out is the same polarity as data

in. The output is in the high-impedance (floating) state until

CAS\ and OE\ are brought low. In a read cycle the output

becomes valid after all access times are satisfied. The output

remains valid while CAS\ and OE\ are low. CAS\ or OE\ going

high returns it to the high-impedance state.

Output Enable (OE\)

OE\ controls the impedance of the output buffers. When

OE\ is high, the buffers remain in the high-impedance state.

Bringing OE\ low during a normal cycle activates the output

buffers, putting them in the low-impedance state. It is

necessary for both RAS\ and CAS\ to be brought low for the

output buffers to go into the low-impedance state. Once in

the low-ompedance state, they remain in the low-impedance

state until either OE\ or CAS\ is brought high.

Refresh

A refresh operation must be performed at least once every

16ms to retain data. This can be achieved by strobing each of

the 1024 rows (A0-A9). A normal read or write cycle

refreshes all bits in each row that is selected. A RAS\-only

operation can be used by holding CAS\ at the high (inactive)

level, conserving power as the output buffer remains in the

high-impedance state. Externally generated addresses must

be used for a RAS\-only refresh. Hidden refresh can be

performed while maintaining valid data at teh output pin. This

is accomplished by holding CAS\ at V

IL

after a read operation

and cycling RAS\ after a specified precharge period, similar

to a RAS\-only refresh cycle. The external address is ignored

during the hidden refresh cycles.

CAS\-before-RAS\ (CBR) and hidden refresh

CBR refresh is utilized by bringing CAS\ low earlier than

RAS\ (see parameter t

CSR

) and holding it low after RAS\ falls

(see parameter t

CSR

). For successive CBR refresh cycles,

CAS\ can remain low while cycling RAS\. The external

address is ignored and the refresh address is generated

internally. During CBR refresh cycles the outputs remain in

the high-impedance state.

Hidden refresh can be performed while maintaining valid

data at the output pins. Thsi is accomplished by holding CAS\

at VIL after a read operation. RAS\ is cycled after the

specified read cycle parameters are met. Hidden refresh can

also be used in conjuction with an early-write cycle. CAS\ is

maintained at VIL while RAS\ is cycled, once all the specified

early-write parameters are met. Externally generated

addresses must be used to specify the location to be accessed

during the initial RAS\ cycle of a hidden refresh operation.

Subsequent RAS\ cycles (refresh cycles) use the internally-

generated addresses and the external address is ignored.

Power Up

To achieve proper device operation, an initial pause of

200µs followed by a minimum of eight initialization cycles is