ASAHI KASEI

[AK5354]

MS0054-E-02

2004/12

- 11 -

Timing of Control Register

The internal registers are written by the 3-wire

µP interface pins: CSN, CCLK, CDTI. These data are included by Op-code

(3bit), Address (LSB-first, 5bit) and Control data (LSB-first, 8bit). A side of transmitted data is output to each bit by “

↓”

of CCLK, a side of receiving data is input by “

↑” of CCLK. Writing of data becomes effective by “↑” of CSN. CSN

should be held to “H” at no access.

Address except 00H

∼ 03H inhibits control of writing. And CCLK always need 16 edges of “↑” during CSN = “L”.

CSN

CCLK

01

2

34

5

67

8

9

10

11 12 13 14 15

CDTI

op0 op1

A2

A1

A3 A4

A0

D0 D1 D2D3D4 D5D6 D7

op2

op0-op2: Op code (Fixed to “**1:WRITE”)

A0-A4:

Register Address

D0-D7:

Control data

“1”

“*”

“*”

Figure 9. Control Data Timing

Register Map

Addr

Register Name

D7

D6

D5

D4

D3

D2

D1

D0

00H

Input Select

0

0

0

HPF

RIN2

RIN1

LIN2

LIN1

01H

Mode Control 1

0

0

0

0

0

0

PM1

PM0

02H

Mode Control 2

MONO1

MONO0

ZTM1

ZTM0

0

0

DIF

0

03H

Input Analog PGA Control

ZEIP

IPGA6

IPGA5

IPGA4

IPGA3

IPGA2

IPGA1

IPGA0

All registers are reset at PDN = “L”, then inhibits writing to all registers.