MC100LVEL56

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2

D0b

D0b

D1a

17

18

16

15

14

13

12

4

3

5

678

9

Q0

11

10

SEL0

Q1

Q1

D0a

19

20

2

1

Q0

D1a

D0a

D1b

D1b

10

1

0

Table 1. PIN DESCRIPTION

PIN

D0a* − D1a*

D0a* − D1a*

ECL Input Data a Invert

FUNCTION

ECL Input Data a

D0b* − D1b*

D0b* − D1b*

ECL Input Data b Invert

ECL Input Data b

SEL0* − SEL1*

COM_SEL*

ECL Common Select Input

ECL Indiv. Select Input

Q0 − Q1

ECL True Outputs

Output Reference Voltage

Q0 − Q1

ECL Inverted Outputs

Positive Supply

Negative Supply

SEL0

X

L

L

H

H

Table 2. TRUTH TABLE

Q0,

Q0

a

b

b

a

a

SEL1

X

L

H

H

L

COM_SEL

H

L

L

L

L

Q1,

Q1

a

b

a

a

b

to Power Supply to guarantee proper operation.

Figure 1. 20-Lead Package (Top View) and Logic Diagram

* Pins will default LOW when left open.

Table 3. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

75 KW

Internal Input Pullup Resistor

N/A

ESD Protection

Human Body Model

Machine Model

Device Model

> 2 kV

> 200 V

> 4 kV

Moisture Sensitivity, (Note 1)

Pb-Free

Level 3

Flammability Rating

Oxygen Index

UL 94 V−0 @ 0.125 in

28 to 34

Transistor Count

147

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.