MC100LVEL90DWG datasheet(4/5 Pages) ONSEMI

부품명	MC100LVEL90DWG

상세설명	-3.3V / -5V Triple ECL Input to LVPECL Output Translator

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MC100LVEL90

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Table 5. AC CHARACTERISTICS (VCC = 3.0 V to 3.8 V; VEE= −3.0 V to −5.5 V; GND = 0 V)

Symbol

Characteristic

−40°C

25°C

85°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

fmax

Maximum Toggle Frequency

560

650

700

MHz

tPLH

tPHL

Propagation Delay

Diff

D to Q

S.E.

390

340

590

640

420

370

620

670

460

410

660

710

ps

tSKEW

Skew

Output-to-Output (Note 1)

Part-to-Part (Diff) (Note 1)

Duty Cycle (Diff) (Note 2)

20

25

100

200

20

25

100

200

20

25

100

200

ps

tJITTER

Random Clock Jitter

TBD

ps

VPP

Input Voltage Swing (Differential Configuration)

(Note 3)

150

1000

150

1000

150

1000

mV

tr

tf

Output Rise/Fall Times Q

(20% − 80%)

230

500

230

500

230

500

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

1. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.

2. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.

3. VPP (min) is swing measured single-ended on each input in differential configuration. The device has a DC gain of ≈40.

Figure 2. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

QD

Q

D

Zo = 50 W

50 W

VTT

VTT = VCC − 2.0 V

Resource Reference of Application Notes

AN1405/D

− ECL Clock Distribution Techniques

AN1406/D

− Designing with PECL (ECL at +5.0 V)

AN1503/D

− ECLinPS I/O SPiCE Modeling Kit

AN1504/D

− Metastability and the ECLinPS Family

AN1568/D

− Interfacing Between LVDS and ECL

AN1672/D

− The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

유사한 부품 번호 - MC100LVEL90DWG

제조업체	부품명	데이터시트	상세설명
ON Semiconductor	MC100LVEL90DWG	112Kb / 6P	??.3V / ??V Triple ECL Input to LVPECL Output Translator November, 2006 ??Rev. 11

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