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SI3021-KT 데이터시트(PDF) 8 Page - List of Unclassifed Manufacturers |
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SI3021-KT 데이터시트(HTML) 8 Page - List of Unclassifed Manufacturers |
8 / 54 page Si 30 35 8 Rev. 1.2 Figure 3. Serial Interface Timing Diagram Table 8. Switching Characteristics—Serial Interface (DCE = 0) (VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF) Parameter Symbol Min Typ Max Unit Cycle time, SCLK tc 354 1/256 Fs — ns SCLK duty cycle tdty —50 — % Delay time, SCLK ↑ to FSYNC ↓ td1 —— 10 ns Delay time, SCLK ↑ to SDO valid td2 —— 20 ns Delay time, SCLK ↑ to FSYNC ↑ td3 —— 10 ns Setup time, SDI before SCLK ↓ tsu 25 — — ns Hold time, SDI after SCLK ↓ th 20 — — ns Setup time, FC ↑ before SCLK ↑ tsfc 40 — — ns Hold time, FC ↑ after SCLK ↑ thfc 40 — — ns Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V SCLK t c t d1 V OH V OL FSYNC (m ode 0) FSYNC (m ode 1) t d3 t d3 t d2 16 Bit SDO 16 Bit SDI D15 D14 D1 D0 D0 D1 D14 D15 t su t h t sfc t hfc FC |
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