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6V49205BPAGI8 데이터시트(PDF) 1 Page - Integrated Device Technology |
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1 / 16 page DATASHEET 6V49205B REVISION R 11/23/16 1 ©2016 Integrated Device Technology, Inc. Freescale P10XX and P20XX System Clock w/Selectable DDR Frequency 6V49205B General Description The 6V49205B is a main clock for Freescale P10xx and P20xx-based systems. It has a selectable System CCB clock and 2 DDRCLK speeds – 100M or 66.66M. The 6V49205B also provides LP-HCSL PCIe outputs for low power and reduced board space. Output Features • 1 - Sys_CCB 3.3V LVCMOS output @ 100M/83.33M/ 80M/66.66M • 1 - DDRCLK 3.3V LVCMOS output @ 100M or 66.66M 1 • 1 - 125M 3.3V LVCMOS output • 6 - LP-HCSL PCIe pairs selectable @ 100M or 125M • 6 - 25MHz 3.3V LVCMOS outputs • 2 - 2.048M 3.3V LVCMOS outputs • 2 - USB 3.3V LVCMOS outputs @12M or 24M Key Specifications • PCIe Gen1-2-3 compliant • <3p rms phase noise on REF outputs Recommended Application System Clock for Freescale P10xx and P20xx-based designs Features • Replaces 11 crystals, 2 oscillators and 3 clock generators; lowers cost, power and area • Integrated terminations on LP-HCSL PCIe outputs; eliminate 24 resistors, saving 41mm2 of board area • Industrial temperature range operation; supports demanding environmental conditions • Advanced 3.3V CMOS process; high-performance, low-power • Supports independent spread spectrum on Sys_CCB/DDRCLK and PCIe outputs • Available in space-saving 7x7mm 48-pin VFQFPN with 0.5mm pad pitch; reduced board space without the need for fine-pitch assembly techniques Block Diagram Note 1 : For DDR Clock: Processor core and I/O supply rails must be ramped with VDD3P3 or earlier. Clock signal will be clamped LOW and output clock will be 100MHz if this is not followed (see diagram below). GND Crystal Oscillator PLL1 (SS) 25MHz Crystal X1 X2 PLL3 (non- SS) REF(5:0) DDRCLK Sys_CCB PLL4 (SS) PCIe_L(5:0) Control Logic SCLK 2.048M(1:0) USB_CLK(2:1) ^FS0 PLL2 (non- SS) 125M ^FS1 ^SEL100#_66 ^SELPCIE125#_100 SDATA 100MHz DDRCLK R40 R39 VDD3P3 10K 10K |
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