6V49205BNLGI8 datasheet(10/16 Pages) IDT

부품명	6V49205BNLGI8

상세설명	Freescale System Clock w/Selectable DDR Frequency

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제조업체	IDT [Integrated Device Technology]

홈페이지	http://www.idt.com

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FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY

10

REVISION R 11/23/16

6V49205B DATASHEET

Byte 0 Frequency and Spread Select Register

Bit

Name

Description

Type

Default

7

SS4

RW

0

6

SS3

RW

0

5

SS2

RW

0

4

SS1

RW

0

3

SS0

RW

0

2

REF_5_EN

Output enable for REF_5

RW

1

REF_4_EN

Output enable for REF_4

RW

1

0

REF_3_EN

Output enable for REF_5

RW

1

Byte 1 Output Enable Register

Bit

Name

Description

Type

Default

7

REF_2_EN

Output enable for REF_2

RW

1

6

REF_1_EN

Output enable for REF_1

RW

1

5

REF_0_EN

Output enable for REF_0

RW

1

4

USB_CLK1_EN

Output enable for USB_CLK1

RW

1

3

USB_CLK2_EN

Output enable for USB_CLK2

RW

1

2

CK2.048_0_EN

Output enable for CK2.048_0

RW

1

CK2.048_1_EN

Output enable for CK2.048_1

RW

1

0

DDRCLK_EN

Output enable for DDRCLK

RW

1

Byte 2 Output Enable Register

Bit

Name

Description

Type

Default

7

Sys_CCB_EN

Output enable for Sys_CCB

RW

1

6

PCIe5_EN

Output enable for PCIe5

RW

1

5

PCIe4_EN

Output enable for PCIe4

RW

1

4

PCIe3_EN

Output enable for PCIe3

RW

1

3

PCIe2_EN

Output enable for PCIe2

RW

1

2

PCIe1_EN

Output enable for PCIe1

RW

1

PCIe0_EN

Output enable for PCIe0

RW

1

0

125M_EN

Output enable for 125M

RW

1

Byte 3 Slew Rate Control Register

Bit

Name

Description

Type

Default

7

USB1_SLEW1

RW

0

6

USB1_SLEW0

RW

1

5

USB2_SLEW1

RW

0

4

USB2_SLEW0

RW

1

3

CK2.048_SLEW1

RW

1

2

CK2.048_SLEW0

RW

1

Sys_CCB_SLEW1

RW

0

Sys_CCB_SLEW0

RW

1

Byte 4 Slew Rate Control Register

Bit

Name

Description

Type

Default

7

DDR_Slew1

RW

0

6

DDR_Slew0

RW

1

5

0

4

1

3FS1

RW

Latch

2FS0

RW

Latch

1

USB1_fSel

USB_CLK1 Clock Frequency Select

RW

0

USB2_fSel

USB_CLK2 Clock Frequency Select

RW

1

Byte 5 is Reserved

Sys_CCB and DDRCLK Spread

Selection Table

See Table 2: Sys_CCB and DDRCLK

Spread Table

DDRCLK Slew Rate Control

See DDR Electrical Tables

Sys_CCB Frequency Select Latch

See Table 3: Sys_CCB Frequency

Selection

12MHz

24MHz

12MHz

24MHz

Reserved

CK2.048_0 and CK2.048_1 Slew Rate

Control

See CK2.048 Electrical Tables

Sys_CCB Slew Rate Control

See Sys_CCB Electrical Tables

01

USB_CLK1 Slew Rate Control

See USB Electrical Tables

USB_CLK2 Slew Rate Control

See USB Electrical Tables

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

01

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

01

Output Disabled

Output Enabled

Output Disabled

Output Enabled

PCIE Spread Selection Table

See Table 1: PCIE Spread Table

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

01

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

Output Disabled

Output Enabled

유사한 부품 번호 - 6V49205BNLGI8

제조업체	부품명	데이터시트	상세설명
Integrated Device Techn...	6V49205BNLGI8	558Kb / 18P	Freescale P10XX and P20XX System Clock
Renesas Technology Corp	6V49205BNLGI8	802Kb / 18P	Freescale P10XX and P20XX System Clock with Selectable DDR Frequency SEPTEMBER 29, 2021

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유사한 설명 - 6V49205BNLGI8

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Renesas Technology Corp	6V49205B	802Kb / 18P	Freescale P10XX and P20XX System Clock with Selectable DDR Frequency SEPTEMBER 29, 2021
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