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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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9ZXL1950 데이터시트(PDF) 8 Page - Integrated Device Technology |
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9ZXL1950 데이터시트(HTML) 8 Page - Integrated Device Technology |
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8 / 18 page  19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 8 REVISION E 11/20/15 9ZXL1950 DATASHEET Electrical Characteristics–Skew and Differential Jitter Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES CLK_IN, DIF[x:0] tSPO_PLL Input-to-Output Skew in PLL mode nominal value @ 35°C, 3.3V, 100MHz -150 -117 -50 ps 1,2,4,5,8 CLK_IN, DIF[x:0] tPD_BYP Input-to-Output Skew in Bypass mode nominal value @ 35°C, 3.3V 2.5 3.6 4.5 ns 1,2,3,5,8 CLK_IN, DIF[x:0] tDSPO_PLL Input-to-Output Skew Varation in PLL mode across voltage and temperature -50 0 50 ps 1,2,3,5,8 CLK_IN, DIF[x:0] tDSPO_BYP Input-to-Output Skew Varation in Bypass mode across temperature for a given voltage -250 0 250 ps 1,2,3,5,8 CLK_IN, DIF[x:0] tDTE Random Differential Tracking error beween two 9ZX devices in Hi BW Mode 15 ps (rms) 1,2,3,5,8 CLK_IN, DIF[x:0] tDSSTE Random Differential Spread Spectrum Tracking error beween two 9ZX devices in Hi BW Mode 5 75 ps 1,2,3,5,8 DIF[x:0] tSKEW_ALL Output-to-Output Skew across all outputs (Common to Bypass and PLL mode). 100MHz 37 50 ps 1,2,3,8 PLL Jitter Peaking jpeak-hibw LOBW#_BYPASS_HIBW = 1 0 1.8 2.5 dB 7,8 PLL Jitter Peaking jpeak-lobw LOBW#_BYPASS_HIBW = 0 0 0.7 2 dB 7,8 PLL Bandwidth pllHIBW LOBW#_BYPASS_HIBW = 1 2 3.3 4 MHz 8,9 PLL Bandwidth pllLOBW LOBW#_BYPASS_HIBW = 0 0.7 1.2 1.4 MHz 8,9 Duty Cycle tDC Measured differentially, PLL Mode 45 50 55 % 1 Duty Cycle Distortion tDCD Measured differentially, Bypass Mode @100MHz 0 0.7 1.5 % 1,10 PLL mode 12 50 ps 1,11 Additive Jitter in Bypass Mode 0 10 ps 1,11 Notes for preceding table: 6. t is the period of the input clock 7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 8. Guaranteed by design and characterization, not 100% tested in production. 9 Measured at 3 db down or half power point. 10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 11 Measured from differential waveform 1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. 3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4 This parameter is deterministic for a given device 5 Measured with scope averaging on to find mean value. Jitter, Cycle to cycle tjcyc-cyc |
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