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LM2733XMFX 데이터시트(PDF) 11 Page - National Semiconductor (TI) |
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LM2733XMFX 데이터시트(HTML) 11 Page - National Semiconductor (TI) |
11 / 13 page Application Hints (Continued) MAXIMUM SWITCH CURRENT The maximum FET swtch current available before the cur- rent limiter cuts in is dependent on duty cycle of the appli- cation. This is illustrated in the graphs below which show both the typical and guaranteed values of switch current for both the "X" and "Y" versions as a function of effective (actual) duty cycle: 20055425 Switch Current Limit vs Duty Cycle - "X" 20055426 Switch Current Limit vs Duty Cycle - "Y" CALCULATING LOAD CURRENT As shown in the figure which depicts inductor current, the load current is related to the average inductor current by the relation: I LOAD =IIND(AVG) x (1 - DC) Where "DC" is the duty cycle of the application. The switch current can be found by: I SW =IIND(AVG) + 1 ⁄2 (I RIPPLE) Inductor ripple current is dependent on inductance, duty cycle, input voltage and frequency: I RIPPLE =DCx(VIN-VSW)/(fxL) combining all terms, we can develop an expression which allows the maximum available load current to be calculated: The equation shown to calculate maximum load current takes into account the losses in the inductor or turn-OFF switching losses of the FET and diode. For actual load current in typical applications, we took bench data for vari- ous input and output voltages for both the "X" and "Y" versions of the LM2733 and displayed the maximum load current available for a typical device in graph form: 20055434 Max. Load Current vs V IN - "X" 20055433 Max. Load Current vs V IN - "Y" DESIGN PARAMETERS V SW AND ISW The value of the FET "ON" voltage (referred to as V SW in the equations) is dependent on load current. A good approxima- tion can be obtained by multiplying the "ON Resistance" of the FET times the average inductor current. FET on resistance increases at V IN values below 5V, since the internal N-FET has less gate voltage in this input voltage range (see Typical performance Characteristics curves). Above V IN = 5V, the FET gate voltage is internally clamped to 5V. www.national.com 11 |
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