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FM25160-S 데이터시트(PDF) 4 Page - List of Unclassifed Manufacturers

부품명 FM25160-S
상세설명  16Kb FRAM Serial Memory
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Ramtron
FM25160
12 May 2000
4/14
power-on reset. It is the user’s responsibility to ensure
that VCC is within data sheet tolerances to prevent
incorrect operation.
Serial Peripheral Interface – SPI Bus
The FM25160 employs a Serial Peripheral Interface
(SPI) bus. This high-speed serial bus is provides high
performance
serial
communication
to
a
host
microcontroller.
Many
common
microcontrollers
have hardware SPI ports allowing a direct interface. It
is quite simple to emulate the port using ordinary port
pins for microcontrollers that do not. Note that the
FM25160 operates in SPI Mode 0 only.
The SPI interface uses a total of four pins, clock,
data-in, data-out, and chip select. It is possible to
connect the two data lines together. Figure 2
illustrates a typical system configuration using the
FM25160 with a microcontroller that offers an SPI
port. Figure 3 shows a similar configuration for a
microcontroller that has no hardware support for the
SPI bus.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data lines. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25160 will begin monitoring
the clock and data lines. The relationship between the
falling edge of \CS, the clock and data is dictated by
the SPI mode. There are four such modes however
the FM25160 supports only mode 0. This mode
dictates that the SCK signal must be low when \CS is
activated.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the part. After \CS
is activated, the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer.
The /CS must go inactive after an
operation is complete and before a new op-code can
be issued.
Figure 2. System Configuration with SPI port
Figure 3. System Configuration without SPI port


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