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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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BD37068FV-ME2 데이터시트(PDF) 9 Page - Rohm |
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BD37068FV-ME2 데이터시트(HTML) 9 Page - Rohm |
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9 / 39 page  9/35 BD37068FV-M TSZ02201-0C2C0E100130-1-2 © 2014 ROHM Co., Ltd. All rights reserved. 14.NOV.2016 Rev.002 www.rohm.com TSZ22111・15・001 I 2C-bus Control Signal Specification 1. Electrical specifications and timing for bus lines and I/O stages Figure 12. Definition of timing on the I 2C-bus Table 1 Characteristics of the SDA and SCL bus lines for I 2C-bus devices Parameter Symbol Fast-mode I 2C-bus Unit Min Max 1 SCL Clock Frequency fSCL 0 400 kHz 2 Bus Free time between a STOP and START condition tBUF 1.3 － μsec 3 Hold Time (repeated) START condition. After this period, the first clock pulse is generated tHD;STA 0.6 － μsec 4 LOW Period of the SCL Clock tLOW 1.3 － μsec 5 HIGH Period of the SCL Clock tHIGH 0.6 － μsec 6 Set-up time for a Repeated START Condition tSU;STA 0.6 － μsec 7 Data Hold Time tHD;DAT 0* － μsec 8 Data set-up Time tSU;DAT 100 － nsec 9 Set-up Time for STOP Condition tSU;STO 0.6 － μsec All values referred to VIH min. and VIL max. Levels (see Table 2). Table 2 Characteristics of the SDA and SCL I/O stages for I 2C-bus devices Parameter Symbol Fast-mode I 2C-bus Unit Min Max 10 LOW level input voltage: Fixed input levels VIL -0.5 +1 V 11 HIGH level input voltage: Fixed input levels VIH 2.3 - V 12 Pulse width of spikes, which must be suppressed by the input filter. tSP 0 50 nsec 13 LOW level output voltage (open drain or open collector): At 3mA sink current VOL1 0 0.4 V 14 Input current each I/O pin with an input voltage between 0.4V and 0.9 VDD max. Ii -10 +10 μA SCL SDA ｔ BUF ： 4 µsec ｔ HD; STA ： 2 µsec ｔ HD; DAT ： 1µsec ｔ LOW ： 3 µsec ｔ HIGH ： 1 µsec ｔ SU; DAT ： 1µsec ｔ SU; STO ： 2 µsec SDA S SCL tLOW tHD;DAT P tHD;STA tHIGH tBUF tSU;DAT tSU;STA T tSU;STO T tSP tHD;STA T Sr P Figure 13. I 2C data transmission timing SCL clock frequency:250kHz |
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