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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 29 Page - Microchip Technology

๋ถ€ํ’ˆ๋ช… LAN9117
์ƒ์„ธ๋‚ด์šฉ  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 29 Page - Microchip Technology

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DS00002267A-page 29
LAN9117
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the
E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not
respond within 30ms.
Table 3-8, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for each EEPROM
operation.
3.9.2.2
MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register. If a value of 0xA5h
is not found in the first address of the EEPROM, the EEPROM is assumed to be un-programmed and MAC Address
Reload operation will fail. The โ€œMAC Address Loadedโ€ bit indicates a successful load of the MAC address. The EPC_-
LOAD bit is set after a successful reload of the MAC address.
3.9.2.3
EEPROM Command and Data Registers
Refer to Section 5.3.23, "E2P_CMD โ€“ EEPROM Command Register," on page 77 and Section 5.3.24, "E2P_DATA โ€“
EEPROM Data Register," on page 79 for a detailed description of these registers. Supported EEPROM operations are
described in these sections.
3.9.2.4
EEPROM Timing
Refer to Section 6.9, "EEPROM Timing," on page 104 for detailed EEPROM timing specifications.
FIGURE 3-10:
EEPROM WRAL CYCLE
TABLE 3-8:
REQUIRED EECLK CYCLES
Operation
Required EECLK Cycles
ERASE
10
ERAL
10
EWDS
10
EWEN
10
READ
18
WRITE
18
WRAL
18
0
EECLK
EEDIO (INPUT)
EEDIO (OUTPUT)
EECS
1
D7
D0
0
01
t
CSL


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