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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 39 Page - Microchip Technology

๋ถ€ํ’ˆ๋ช… LAN9117
์ƒ์„ธ๋‚ด์šฉ  High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
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LAN9117 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 39 Page - Microchip Technology

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DS00002267A-page 39
LAN9117
Figure 3-14, "TX Buffer Format", shows the TX Buffer as it is written into the LAN9117. It should be noted that not all of
the data shown in this diagram is actually stored in the TX data FIFO. This must be taken into account when calculating
the actual TX data FIFO usage. Please refer to Section 3.13.5, "Calculating Actual TX Data FIFO Usage," on page 42
for a detailed explanation on calculating the actual TX data FIFO usage.
Note 3-15
The LAN9117 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits
wide. Figure 3-14 describes the host write ordering for pairs of atomic 16-bit transactions.
3.13.2
TX COMMAND FORMAT
The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command precedes the data
to be transmitted. The TX command is divided into two, 32-bit words; TX command โ€˜Aโ€™ and TX command โ€˜Bโ€™.
There is a 16-bit packet tag in the TX command โ€˜Bโ€™ command word. Packet tags may, if host software desires, be unique
for each packet (i.e., an incrementing count). The value of the tag will be returned in the RX status word for the associ-
ated packet. The Packet tag can be used by host software to uniquely identify each status word as it is returned to the
host.
Both TX command โ€˜Aโ€™ and TX command โ€˜Bโ€™ are required for each buffer in a given packet. TX command โ€˜Bโ€™ must be
identical for every buffer in a given packet. If the TX command โ€˜Bโ€™ words do not match, the Ethernet controller will assert
the Transmitter Error (TXE) flag.
FIGURE 3-14:
TX BUFFER FORMAT
TX Command 'A'
Offset + Data DWORD0
.
.
.
.
.
Last Data & PAD
0
31
1st
2nd
3rd
Last
Host Write
Order
Optional Pad DWORD0
.
.
.
Optional Pad DWORDn
TX Command 'B'
Optional offset DWORD0
.
.
.
Optional offset DWORDn


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